The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 26, 2024

Filed:

Oct. 13, 2020
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Bok Eng Cheah, Bukit Gambir, MY;

Jackson Chung Peng Kong, Tanjung Tokong, MY;

Min Suet Lim, Simpang Ampat, MY;

Tin Poay Chuah, Bayan Lepas, MY;

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/498 (2006.01); H01L 23/538 (2006.01); H05K 1/14 (2006.01); H05K 1/18 (2006.01); H05K 3/36 (2006.01); H05K 3/46 (2006.01);
U.S. Cl.
CPC ...
H01L 23/4985 (2013.01); H01L 23/49816 (2013.01); H01L 23/5387 (2013.01); H05K 1/144 (2013.01); H05K 1/147 (2013.01); H05K 1/189 (2013.01); H05K 3/361 (2013.01); H05K 3/4697 (2013.01); H05K 2201/10378 (2013.01);
Abstract

To address the issue of shrinking volume that can be allocated for electrical components, a system can use an interposer with a flexible portion. A first portion of the interposer can electrically connect to a top side of a motherboard. A flexible portion of the interposer, adjacent to the first portion, can wrap around an edge of the motherboard. A peripheral portion of the interposer, adjacent to the flexible portion, can electrically connect to a bottom side of the motherboard. The peripheral portion can be flexible or rigid. The interposer can define a cavity that extends through the first portion of the interposer. A chip package can electrically connect to the first portion of the interposer. The chip package can be coupled to at least one electrical component that extends into the cavity when the chip package is connected to the interposer.


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