The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 26, 2024

Filed:

Jun. 15, 2021
Applicant:

Applied Materials, Inc., Santa Clara, CA (US);

Inventors:

Armin Saeedi Vahdat, Burlington, MA (US);

Tristan Y. Ma, Lexington, MA (US);

Johannes M. van Meer, Middleton, MA (US);

John Hautala, Beverly, MA (US);

Naushad K. Variam, Marblehead, MA (US);

Assignee:

Applied Materials, Inc., Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/768 (2006.01); H01L 21/02 (2006.01); H01L 21/764 (2006.01);
U.S. Cl.
CPC ...
H01L 21/7682 (2013.01); H01L 21/0226 (2013.01); H01L 21/764 (2013.01);
Abstract

Disclosed are approaches for forming semiconductor device cavities using directional dielectric deposition. One method may include providing a plurality of semiconductor structures and a plurality of trenches of a semiconductor device, and forming a dielectric atop the plurality of semiconductor structures by delivering a dielectric material at a non-zero angle of inclination relative to a normal extending perpendicular from a top surface of the plurality of semiconductor structures. The dielectric may be further formed by delivering the dielectric material at a second non-zero angle of inclination relative to the normal extending perpendicular from the top surface of the plurality of semiconductor structures.


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