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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 11935894 B1

PDFFull Text
Date of Patent:
Mar. 19, 2024

Filed:

Nov. 04, 2022

Integrated circuit device with improved layout

Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsin-Chu, TW;

Inventors:

Fong-yuan Chang, Hsin-Chu, TW;

Chun-Chen Chen, Hsin-Chu, TW;

Po-Hsiang Huang, Tainan, TW;

Lee-Chung Lu, Taipei, TW;

Chung-Te Lin, Tainan, TW;

Jerry Chang Jui Kao, Taipei, TW;

Sheng-Hsiung Chen, Zhubei, TW;

Chin-Chou Liu, Zhubei, TW;

Assignee:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsin-Chu, TW;

Attorney:

Duane Morris LLP

Primary Examiner:

Mark W Tornow

Assistant Examiner:

Priya M Rampersaud

Int. Cl.
CPC ...
H01L 27/118 (2006.01); G06F 30/398 (2020.01); H01L 27/02 (2006.01);
U.S. Cl.
CPC ...
H01L 27/11807 (2013.01); G06F 30/398 (2020.01); H01L 27/0207 (2013.01); H01L 2027/11862 (2013.01); H01L 2027/11866 (2013.01); H01L 2027/11875 (2013.01); H01L 2027/11881 (2013.01); H01L 2027/11885 (2013.01);
Abstract

An integrated circuit device includes a device layer having devices spaced in accordance with a predetermined device pitch, a first metal interconnection layer disposed above the device layer and coupled to the device layer, and a second metal interconnection layer disposed above the first metal interconnection layer and coupled to the first metal interconnection layer through a first via layer. The second metal interconnection layer has metal lines spaced in accordance with a predetermined metal line pitch, and a ratio of the predetermined metal line pitch to predetermined device pitch is less than 1.

Find Patent Forward Citations

Chang, Fong-yuan. (2024). Integrated circuit device with improved layout (U.S. Patent No. 11935894). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/11935894

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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