The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 19, 2024

Filed:

Apr. 10, 2023
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;

Inventors:

Tzu-Sung Huang, Tainan, TW;

Ming Hung Tseng, Toufen Township, TW;

Yen-Liang Lin, Taichung, TW;

Hao-Yi Tsai, Hsinchu, TW;

Chi-Ming Tsai, New Taipei, TW;

Chung-Shi Liu, Hsinchu, TW;

Chih-Wei Lin, Zhubei, TW;

Ming-Che Ho, Tainan, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/31 (2006.01); H01L 21/56 (2006.01); H01L 21/768 (2006.01); H01L 23/16 (2006.01); H01L 23/522 (2006.01); H01L 23/528 (2006.01);
U.S. Cl.
CPC ...
H01L 23/3157 (2013.01); H01L 21/56 (2013.01); H01L 21/76802 (2013.01); H01L 21/76843 (2013.01); H01L 23/16 (2013.01); H01L 23/5226 (2013.01); H01L 23/528 (2013.01);
Abstract

In an embodiment, a device includes: an integrated circuit die; an encapsulant at least partially surrounding the integrated circuit die, the encapsulant including fillers having an average diameter; a through via extending through the encapsulant, the through via having a lower portion of a constant width and an upper portion of a continuously decreasing width, a thickness of the upper portion being greater than the average diameter of the fillers; and a redistribution structure including: a dielectric layer on the through via, the encapsulant, and the integrated circuit die; and a metallization pattern having a via portion extending through the dielectric layer and a line portion extending along the dielectric layer, the metallization pattern being electrically coupled to the through via and the integrated circuit die.


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