The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 19, 2024

Filed:

Jul. 07, 2022
Applicant:

Micron Technology, Inc., Boise, ID (US);

Inventors:

Vamsi Pavan Rayaprolu, Santa Clara, CA (US);

Mustafa N. Kaynak, San Diego, CA (US);

Sivagnanam Parthasarathy, Carlsbad, CA (US);

Patrick Khayat, San Diego, CA (US);

Sampath Ratnam, San Jose, CA (US);

Kishore Kumar Muchherla, Fremont, CA (US);

Jiangang Wu, Milpitas, CA (US);

James Fitzpatrick, Laguna Niguel, CA (US);

Assignee:

Micron Technology, Inc., Boise, ID (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 29/00 (2006.01); G06F 11/07 (2006.01); G06F 11/10 (2006.01);
U.S. Cl.
CPC ...
G06F 11/1068 (2013.01); G06F 11/076 (2013.01); G06F 11/0772 (2013.01);
Abstract

Systems and methods are disclosed including a memory device and a processing device operatively coupled to the memory device. The processing device can perform operations comprising selecting a source set of memory cells of the memory device, wherein the source set of memory cells are configured to store a first number of bits per memory cell; performing a data integrity check on the source set of memory cells to obtain a data integrity metric value; determining whether the data integrity metric value satisfies a threshold criterion; and responsive to determining that the data integrity metric value fails to satisfy the threshold criterion, causing the memory device to copy data from the source set of memory cells to a destination set of memory cells of the memory device, wherein the destination set of memory cells are configured to store a second number of bits per memory cell.


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