The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 12, 2024
Filed:
Mar. 09, 2023
Applicant:
Nexgen Power Systems, Inc., Santa Clara, CA (US);
Inventors:
Clifford Drowley, Santa Clara, CA (US);
Andrew P. Edwards, Santa Clara, CA (US);
Subhash Srinivas Pidaparthi, Santa Clara, CA (US);
Ray Milano, Santa Clara, CA (US);
Assignee:
Nexgen Power Systems, Inc., Santa Clara, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/808 (2006.01); H01L 27/06 (2006.01); H01L 27/088 (2006.01); H01L 29/06 (2006.01); H01L 29/20 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01);
U.S. Cl.
CPC ...
H01L 29/8083 (2013.01); H01L 27/0676 (2013.01); H01L 27/0886 (2013.01); H01L 29/0642 (2013.01); H01L 29/2003 (2013.01); H01L 29/66909 (2013.01); H01L 29/785 (2013.01);
Abstract
Methods and semiconductor devices are provided. A vertical junction field effect transistor (JFET) includes a substrate, an active region having a plurality of semiconductor fins, a source metal layer on an upper surface of the fins, a source metal pad layer coupled to the semiconductor fins through the source metal layer, a gate region surrounding the semiconductor fins, and a body diode surrounding the gate region.