The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 27, 2024
Filed:
May. 24, 2021
Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;
Chih-Liang Chen, Hsinchu, TW;
Cheng-Chi Chuang, New Taipei, TW;
Chih-Ming Lai, Hsinchu, TW;
Chia-Tien Wu, Taichung, TW;
Charles Chew-Yuen Young, Cupertino, CA (US);
Hui-Ting Yang, Zhubei, TW;
Jiann-Tyng Tzeng, Hsinchu, TW;
Ru-Gun Liu, Zhubei, TW;
Wei-Cheng Lin, Taichung, TW;
Lei-Chun Chou, Taipei, TW;
Wei-An Lai, Hsinchu, TW;
Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;
Abstract
The present disclosure describes an apparatus with a local interconnect structure. The apparatus can include a first transistor, a second transistor, a first interconnect structure, a second interconnect structure, and a third interconnect structure. The local interconnect structure can be coupled to gate terminals of the first and second transistors and routed at a same interconnect level as reference metal lines coupled to ground and a power supply voltage. The first interconnect structure can be coupled to a source/drain terminal of the first transistor and routed above the local interconnect structure. The second interconnect structure can be coupled to a source/drain terminal of the second transistor and routed above the local interconnect structure. The third interconnect structure can be routed above the local interconnect structure and at a same interconnect level as the first and second interconnect structures.