The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 20, 2024

Filed:

Aug. 23, 2021
Applicant:

Fujian Jinhua Integrated Circuit Co., Ltd., Quanzhou, CN;

Inventors:

Yu-Cheng Tung, Kaohsiung, TW;

Janbo Zhang, Zhangzhou, CN;

Shih-Han Hung, Kaohsiung, TW;

Li-Wei Feng, Tainan, TW;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H10B 12/00 (2023.01);
U.S. Cl.
CPC ...
H10B 12/482 (2023.02); H10B 12/315 (2023.02); H10B 12/34 (2023.02);
Abstract

The invention discloses a semiconductor memory device, which is characterized by comprising a substrate defining a cell region and an adjacent periphery region, a plurality of bit lines are arranged on the substrate and arranged along a first direction, each bit line comprises a conductive part, and the bit line comprises four sidewalls, and a spacer surrounds the four sidewalls of the bit line, the spacer comprises two short spacers covering two ends of the conductive part, two long spacers covering the two long sides of the conductive part, and a plurality of storage node contact isolations located between any two adjacent bit lines, at least a part of the storage node contact isolations cover directly above the spacers. The structure of the invention can improve the electrical isolation effect, preferably avoid leakage current and improve the quality of components.


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