The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 20, 2024

Filed:

Jun. 15, 2020
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Kirby Maxey, Hillsboro, OR (US);

Chelsey Dorow, Portland, OR (US);

Kevin P. O'Brien, Portland, OR (US);

Carl Naylor, Portland, OR (US);

Ashish Verma Penumatcha, Beaverton, OR (US);

Tanay Gosavi, Portland, OR (US);

Uygar E. Avci, Portland, OR (US);

Shriram Shivaraman, Hillsboro, OR (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/786 (2006.01); H01L 29/423 (2006.01); H01L 29/66 (2006.01); H01L 29/24 (2006.01);
U.S. Cl.
CPC ...
H01L 29/78696 (2013.01); H01L 29/24 (2013.01); H01L 29/42392 (2013.01); H01L 29/66969 (2013.01);
Abstract

Embodiments include two-dimensional (2D) semiconductor sheet transistors and methods of forming such devices. In an embodiment, a semiconductor device comprises a stack of 2D semiconductor sheets, where individual ones of the 2D semiconductor sheets have a first end and a second end opposite from the first end. In an embodiment, a first spacer is over the first end of the 2D semiconductor sheets, and a second spacer is over the second end of the 2D semiconductor sheets. Embodiments further comprise a gate electrode between the first spacer and the second spacer, a source contact adjacent to the first end of the 2D semiconductor sheets, and a drain contact adjacent to the second end of the 2D semiconductor sheets.


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