The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 20, 2024

Filed:

Jan. 06, 2021
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Ting-Li Yang, Tainan, TW;

Po-Hao Tsai, Taoyuan, TW;

Ching-Wen Hsiao, Hsinchu, TW;

Hong-Seng Shue, Hsinchu County, TW;

Yu-Tse Su, Chiayi, TW;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/768 (2006.01); H01L 23/522 (2006.01); H01L 23/00 (2006.01); H01L 23/31 (2006.01); H01L 23/495 (2006.01); H01L 23/528 (2006.01); H01L 23/532 (2006.01); H01L 25/065 (2023.01); H01L 21/48 (2006.01);
U.S. Cl.
CPC ...
H01L 23/5226 (2013.01); H01L 21/486 (2013.01); H01L 21/4853 (2013.01); H01L 21/76877 (2013.01); H01L 23/528 (2013.01); H01L 24/14 (2013.01);
Abstract

A chip structure is provided. The chip structure includes a substrate. The chip structure includes a conductive line over the substrate. The chip structure includes a first passivation layer over the substrate and the conductive line. The chip structure includes a conductive pad over the first passivation layer covering the conductive line. The conductive pad is thicker and wider than the conductive line. The chip structure includes a first conductive via structure and a second conductive via structure passing through the first passivation layer and directly connected between the conductive pad and the conductive line. The chip structure includes a conductive pillar over the conductive pad.


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