The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 20, 2024

Filed:

Nov. 21, 2022
Applicant:

Taiwan Semiconductor Manufacturing Company Ltd., Hsinchu, TW;

Inventors:

Yi-Jing Lee, Hsinchu, TW;

Ya-Yun Cheng, Taichung, TW;

Hau-Yu Lin, Kaohsiung, TW;

I-Sheng Chen, Taipei, TW;

Chia-Ming Hsu, Hualien County, TW;

Chih-Hsin Ko, Kaohsiung County, TW;

Clement Hsingjen Wann, Carmel, NY (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/00 (2006.01); H01L 21/8238 (2006.01); H01L 27/092 (2006.01); H01L 29/49 (2006.01); H01L 21/321 (2006.01); H01L 21/02 (2006.01); H01L 21/28 (2006.01); H01L 29/66 (2006.01);
U.S. Cl.
CPC ...
H01L 21/823842 (2013.01); H01L 21/02068 (2013.01); H01L 21/28088 (2013.01); H01L 21/321 (2013.01); H01L 27/0922 (2013.01); H01L 29/4966 (2013.01); H01L 29/66545 (2013.01);
Abstract

A method includes: providing a first gate electrode over the substrate; forming a first pair of spacers on two sides of the first gate electrode; removing the first gate electrode to form a first trench between the first pair of spacers; depositing a dielectric layer in the first trench; depositing a first layer over the dielectric layer; removing the first layer from the first trench; and depositing a work function layer over the dielectric layer in the first trench.


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