The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 13, 2024

Filed:

May. 13, 2022
Applicant:

Kioxia Corporation, Tokyo, JP;

Inventors:

Masaru Kito, Yokohama, JP;

Hideaki Aochi, Kawasaki, JP;

Ryota Katsumata, Yokohama, JP;

Akihiro Nitayama, Yokohama, JP;

Masaru Kidoh, Kawasaki, JP;

Hiroyasu Tanaka, Tokyo, JP;

Yoshiaki Fukuzumi, Yokohama, JP;

Yasuyuki Matsuoka, Yokohama, JP;

Mitsuru Sato, Yokohama, JP;

Assignee:

Kioxia Corporation, Tokyo, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10B 43/27 (2023.01); H01L 21/822 (2006.01); H01L 27/06 (2006.01); H01L 27/105 (2023.01); H10B 41/27 (2023.01); H10B 43/20 (2023.01); H10B 43/40 (2023.01); H10B 69/00 (2023.01); G11C 16/04 (2006.01);
U.S. Cl.
CPC ...
H10B 43/27 (2023.02); H01L 21/8221 (2013.01); H01L 27/0688 (2013.01); H01L 27/105 (2013.01); H10B 41/27 (2023.02); H10B 43/20 (2023.02); H10B 43/40 (2023.02); H10B 69/00 (2023.02); G11C 16/0483 (2013.01);
Abstract

A nonvolatile semiconductor memory device that have a new structure are provided, in which memory cells are laminated in a three dimensional state so that the chip area may be reduced. The nonvolatile semiconductor memory device of the present invention is a nonvolatile semiconductor memory device that has a plurality of the memory strings, in which a plurality of electrically programmable memory cells is connected in series. The memory strings comprise a pillar shaped semiconductor; a first insulation film formed around the pillar shaped semiconductor; a charge storage layer formed around the first insulation film; the second insulation film formed around the charge storage layer; and first or nth electrodes formed around the second insulation film (n is natural number more than 1). The first or nth electrodes of the memory strings and the other first or nth electrodes of the memory strings are respectively the first or nth conductor layers that are spread in a two dimensional state.


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