The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 13, 2024

Filed:

Aug. 30, 2021
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Ting-Li Yang, Tainan, TW;

Wen-Hsiung Lu, Tainan, TW;

Lung-Kai Mao, Kaohsiung, TW;

Fu-Wei Liu, Tainan, TW;

Mirng-Ji Lii, Hsinchu County, TW;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/30 (2006.01); H01L 23/48 (2006.01); H01L 21/306 (2006.01); H01L 21/768 (2006.01);
U.S. Cl.
CPC ...
H01L 23/481 (2013.01); H01L 21/30608 (2013.01); H01L 21/76871 (2013.01);
Abstract

A method for forming a semiconductor device structure is provided. The method includes providing a chip structure including a substrate and a wiring structure over a first surface of the substrate. The method includes removing a first portion of the wiring structure adjacent to the hole to widen a second portion of the hole in the wiring structure. The second portion has a first width increasing in a first direction away from the substrate. The method includes forming a first seed layer over the wiring structure and in the hole. The method includes thinning the substrate from a second surface of the substrate until the first seed layer in the hole is exposed. The method includes forming a second seed layer over the second surface of the substrate and the first seed layer in the hole.


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