The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 13, 2024

Filed:

Nov. 04, 2020
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsin-Chu, TW;

Inventors:

Ming-Tung Wu, Hsinchu, TW;

Hsun-Chung Kuang, Hsinchu, TW;

Tung-He Chou, Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/02 (2006.01); B23K 26/53 (2014.01); B23K 26/03 (2006.01); H01L 21/268 (2006.01); H01L 23/544 (2006.01); H01L 21/66 (2006.01); H01L 21/304 (2006.01); B23K 103/00 (2006.01);
U.S. Cl.
CPC ...
H01L 21/02021 (2013.01); B23K 26/032 (2013.01); B23K 26/53 (2015.10); H01L 21/268 (2013.01); H01L 21/3043 (2013.01); H01L 22/20 (2013.01); H01L 23/544 (2013.01); B23K 2103/56 (2018.08); H01L 2223/54426 (2013.01); H01L 2223/54493 (2013.01);
Abstract

In some embodiments, the present disclosure relates to a method that includes aligning a stealth laser apparatus over a wafer using an infrared camera coupled to the stealth laser apparatus. The stealth laser apparatus is used to form a stealth damage region within the wafer that is continuously connected around the wafer and separates an inner region from an outer region of the wafer. The stealth damage region is also arranged at a first distance from an edge of the wafer and extends from a first depth to a second depth beneath a top surface of the wafer. Further, the method includes forming a groove in the wafer to separate the outer region from the inner region of the wafer. The outer region of the wafer is removed using a blade, and a top portion of the inner region of the wafer is removed using a grinding apparatus.


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