The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 30, 2024
Filed:
Sep. 29, 2021
Globalwafers Japan Co., Ltd., Niigata, JP;
Tohoku University, Sendai, JP;
Kazutaka Kamijo, Kitakanbara-gun, JP;
Etsuo Fukuda, Kitakanbara-gun, JP;
Takashi Ishikawa, Kitakanbara-gun, JP;
Koji Izunome, Kitakanbara-gun, JP;
Moriya Miyashita, Kitakanbara-gun, JP;
Takao Sakamoto, Kitakanbara-gun, JP;
Tetsuo Endoh, Sendai, JP;
GLOBALWAFERS JAPAN CO., LTD., Niigata, JP;
TOHOKU UNIVERSITY, Sendai, JP;
Abstract
A method for producing a three-dimensional structure, a method for producing a vertical transistor, a vertical transistor wafer, and a vertical transistor substrate, capable of suppressing the emission of Si due to a heat treatment and making an interface between an oxide film and a core mainly consisting of Si relatively smooth include: forming a three-dimensional shape by processing (for example, by etching) a surface layer of a monocrystalline silicon substrate, the surface layer having an oxygen concentration of 1×10atoms/cmor more; and then forming an oxide film on the surface of the three-dimensional shape by performing a heat treatment. The three-dimensional structure has a shape having projections and recesses in a thickness direction of the silicon substrate, and a height in the thickness direction of the silicon substrate is between 1 nm and 1000 nm, and preferably between 1 nm and 100 nm.