The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 23, 2024

Filed:

Jun. 16, 2020
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsin-Chu, TW;

Inventors:

Yung Feng Chang, Hsinchu, TW;

Bao-Ru Young, Zhubei, TW;

Yu-Jung Chang, Zhubei, TW;

Tzung-Chi Lee, Banciao, TW;

Tung-Heng Hsieh, Zhudong Township, TW;

Chun-Chia Hsu, Kaohsiung, TW;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 27/08 (2006.01); H01L 27/02 (2006.01); H01L 23/52 (2006.01); H01L 29/66 (2006.01); H01L 27/088 (2006.01); H01L 23/528 (2006.01); H01L 21/8234 (2006.01); G06F 30/392 (2020.01); G06F 30/398 (2020.01); G06F 119/02 (2020.01); G06F 119/22 (2020.01);
U.S. Cl.
CPC ...
H01L 27/0207 (2013.01); G06F 30/392 (2020.01); G06F 30/398 (2020.01); H01L 21/823431 (2013.01); H01L 21/823475 (2013.01); H01L 21/823481 (2013.01); H01L 27/0886 (2013.01); H01L 29/66545 (2013.01); G06F 2119/02 (2020.01); G06F 2119/22 (2020.01);
Abstract

An array of poly lines on an active device area of an integrated chip is extended to form a dummy device structure on an adjacent isolation region. The resulting dummy device structure is an array of poly lines having the same line width, line spacing, and pitch as the array of poly lines on the active device area. The poly lines of the dummy device structure are on grid with the poly lines on the active device area. Because the dummy device structure is formed of poly lines that are on grid with the poly lines on the active device area, the dummy device structure may be much closer to the active device area than would otherwise be possible. The resulting proximity of the dummy device structure to the active device area improves anti-dishing performance and reduces empty space on the integrated chip.


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