The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 09, 2024

Filed:

May. 11, 2021
Applicant:

Sandisk Technologies Llc, Addison, TX (US);

Inventors:

Peng Zhang, San Jose, CA (US);

Yanli Zhang, San Jose, CA (US);

Xiang Yang, Santa Clara, CA (US);

Koichi Matsuno, San Jose, CA (US);

Masaaki Higashitani, Cupertino, CA (US);

Johann Alsmeier, San Jose, CA (US);

Assignee:

SANDISK TECHNOLOGIES LLC, Addison, TX (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10B 51/30 (2023.01); H01L 21/764 (2006.01); H01L 29/06 (2006.01); H10B 41/27 (2023.01); H10B 41/35 (2023.01); H10B 43/27 (2023.01); H10B 43/35 (2023.01); H10B 51/20 (2023.01);
U.S. Cl.
CPC ...
H10B 51/30 (2023.02); H01L 21/764 (2013.01); H01L 29/0649 (2013.01); H10B 41/27 (2023.02); H10B 41/35 (2023.02); H10B 43/27 (2023.02); H10B 43/35 (2023.02); H10B 51/20 (2023.02);
Abstract

A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, an array of memory opening fill structures located within an array of memory openings vertically extending through the alternating stack, and a drain-select-level isolation structure vertically extending through drain-select-level electrically conductive layers between two rows of memory opening fill structures. The drain-select-level isolation structure may comprise a low-k dielectric material or an air gap.


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