The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 02, 2024

Filed:

Apr. 12, 2021
Applicant:

Yangtze Memory Technologies Co., Ltd., Wuhan, CN;

Inventors:

Weihua Cheng, Wuhan, CN;

Jun Liu, Wuhan, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10B 10/00 (2023.01); H01L 21/02 (2006.01); H01L 21/20 (2006.01); H01L 21/822 (2006.01); H01L 25/065 (2023.01); G11C 14/00 (2006.01); G11C 16/04 (2006.01); H01L 21/50 (2006.01); H01L 23/00 (2006.01); H01L 25/18 (2023.01); H01L 25/00 (2006.01); H01L 27/06 (2006.01); H01L 29/04 (2006.01); H01L 29/16 (2006.01); H01L 21/76 (2006.01); H10B 12/00 (2023.01); H10B 41/27 (2023.01); H10B 41/40 (2023.01); H10B 43/20 (2023.01); H10B 43/27 (2023.01); H10B 43/35 (2023.01); H10B 43/40 (2023.01);
U.S. Cl.
CPC ...
H10B 10/12 (2023.02); G11C 14/0018 (2013.01); G11C 16/0483 (2013.01); H01L 21/02013 (2013.01); H01L 21/2007 (2013.01); H01L 21/50 (2013.01); H01L 21/76 (2013.01); H01L 21/8221 (2013.01); H01L 24/03 (2013.01); H01L 24/05 (2013.01); H01L 24/06 (2013.01); H01L 24/08 (2013.01); H01L 24/27 (2013.01); H01L 24/29 (2013.01); H01L 24/32 (2013.01); H01L 24/73 (2013.01); H01L 24/83 (2013.01); H01L 24/94 (2013.01); H01L 25/0657 (2013.01); H01L 25/18 (2013.01); H01L 25/50 (2013.01); H01L 27/0688 (2013.01); H01L 29/04 (2013.01); H01L 29/16 (2013.01); H10B 12/02 (2023.02); H10B 12/033 (2023.02); H10B 12/05 (2023.02); H10B 12/09 (2023.02); H10B 12/31 (2023.02); H10B 12/50 (2023.02); H10B 41/27 (2023.02); H10B 41/40 (2023.02); H10B 43/20 (2023.02); H10B 43/27 (2023.02); H10B 43/35 (2023.02); H10B 43/40 (2023.02); H01L 2224/04042 (2013.01); H01L 2224/05569 (2013.01); H01L 2224/08145 (2013.01); H01L 2224/291 (2013.01); H01L 2224/32145 (2013.01); H01L 2224/73215 (2013.01); H01L 2224/80895 (2013.01); H01L 2224/80896 (2013.01); H01L 2224/83895 (2013.01); H01L 2224/83896 (2013.01);
Abstract

First semiconductor structures are formed on a first wafer. At least one of the first semiconductor structures includes a processor, an array of SRAM cells, and a first bonding layer including first bonding contacts. Second semiconductor structures are formed on a second wafer. At least one of the second semiconductor structures includes an array of NAND memory cells and a second bonding layer including second bonding contacts. The first wafer and the second wafer are bonded in a face-to-face manner, such that the at least one of the first semiconductor structures is bonded to the at least one of the second semiconductor structures. The first bonding contacts of the first semiconductor structure are in contact with the second bonding contacts of the second semiconductor structure at a bonding interface. The bonded first and second wafers are diced into dies. At least one of the dies includes the bonded first and second semiconductor structures.


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