The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 02, 2024

Filed:

Dec. 29, 2022
Applicant:

United Microelectronics Corp., Hsinchu, TW;

Inventors:

Hao Che Feng, Kaohsiung, TW;

Hung Jen Huang, Tainan, TW;

Hsin Min Han, Kaohsiung, TW;

Shih-Wei Su, Tainan, TW;

Ming Shu Chiu, Tainan, TW;

Pi-Hung Chuang, Changhua County, TW;

Wei-Hao Huang, New Taipei, TW;

Shao-Wei Wang, Taichung, TW;

Ping Wei Huang, Pingtung County, TW;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/78 (2006.01); H01L 29/06 (2006.01); H01L 21/02 (2006.01); H01L 29/66 (2006.01); H01L 21/3105 (2006.01); H01L 21/311 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7854 (2013.01); H01L 21/0217 (2013.01); H01L 21/02247 (2013.01); H01L 21/31053 (2013.01); H01L 21/31111 (2013.01); H01L 21/31144 (2013.01); H01L 29/0649 (2013.01); H01L 29/66818 (2013.01);
Abstract

The invention provides a method for fabricating a fin structure for fin field effect transistor, including following steps. Providing a substrate, including a fin structure having a silicon fin and a single mask layer just on a top of the silicon fin, the single mask layer being as a top portion of the fin structure. Forming a stress buffer layer on the substrate and conformally covering over the fin structure. Performing a nitridation treatment on the stress buffer layer to have a nitride portion. Perform a flowable deposition process to form a flowable dielectric layer to cover over the fin structures. Annealing the flowable dielectric layer. Polishing the flowable dielectric layer, wherein the nitride portion of the stress buffer layer is used as a polishing stop.


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