The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 02, 2024

Filed:

Feb. 10, 2023
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;

Inventors:

Charles Chew-Yuen Young, Cupertino, CA (US);

Chih-Liang Chen, Hsinchu, TW;

Chih-Ming Lai, Hsinchu, TW;

Jiann-Tyng Tzeng, Hsinchu, TW;

Shun-Li Chen, Tainan, TW;

Kam-Tou Sio, Hsinchu County, TW;

Shih-Wei Peng, Hsinchu, TW;

Chun-Kuang Chen, Hsinchu County, TW;

Ru-Gun Liu, Hsinchu County, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/02 (2006.01); H01L 21/768 (2006.01); H01L 21/8234 (2006.01); H01L 23/485 (2006.01); G06F 30/394 (2020.01); H01L 23/528 (2006.01); H01L 29/66 (2006.01); H01L 21/84 (2006.01);
U.S. Cl.
CPC ...
H01L 27/0207 (2013.01); G06F 30/394 (2020.01); H01L 21/76895 (2013.01); H01L 21/823418 (2013.01); H01L 21/823425 (2013.01); H01L 21/823431 (2013.01); H01L 21/823437 (2013.01); H01L 21/823475 (2013.01); H01L 23/485 (2013.01); H01L 21/76897 (2013.01); H01L 21/845 (2013.01); H01L 23/528 (2013.01); H01L 29/6656 (2013.01); H01L 29/6659 (2013.01); H01L 2924/0002 (2013.01);
Abstract

A method is provided, including the following operations: arranging a first gate structure extending continuously above a first active region and a second active region of a substrate; arranging a first separation spacer disposed on the first gate structure to isolate an electronic signal transmitted through a first gate via and a second gate via that are disposed on the first gate structure, wherein the first gate via and the second gate via are arranged above the first active region and the second active region respectively; and arranging a first local interconnect between the first active region and the second active region, wherein the first local interconnect is electrically coupled to a first contact disposed on the first active region and a second contact disposed on the second active region.


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