The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 02, 2024
Filed:
Apr. 26, 2021
Applicant:
Adeia Semiconductor Inc., San Jose, CA (US);
Inventors:
Javier A. Delacruz, San Jose, CA (US);
Belgacem Haba, Saratoga, CA (US);
Cyprian Emeka Uzoh, San Jose, CA (US);
Rajesh Katkar, Milpitas, CA (US);
Ilyas Mohammed, Santa Clara, CA (US);
Assignee:
Adeia Semiconductor Inc., San Jose, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/00 (2006.01); H01L 25/065 (2023.01);
U.S. Cl.
CPC ...
H01L 25/0652 (2013.01); H01L 24/08 (2013.01); H01L 24/11 (2013.01); H01L 2224/08146 (2013.01); H01L 2224/119 (2013.01); H01L 2224/11464 (2013.01); H01L 2224/13005 (2013.01); H01L 2225/06517 (2013.01); H01L 2225/06544 (2013.01); H01L 2225/06555 (2013.01);
Abstract
An integrated circuit and a method for designing an IC wherein the base or host chip is bonded to smaller chiplets via DBI technology. The bonding of chip to chiplet creates an uneven or multi-level surface of the overall chip requiring a releveling for future bonding. The uneven surface is built up with plating of bumps and subsequently releveled with various methods including planarization.