The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 02, 2024

Filed:

Jun. 09, 2022
Applicant:

Unimicron Technology Corp., Taoyuan, TW;

Inventors:

John Hon-Shing Lau, Taoyuan, TW;

Tzyy-Jang Tseng, Taoyuan, TW;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G02B 6/42 (2006.01); H01S 5/42 (2006.01);
U.S. Cl.
CPC ...
G02B 6/4274 (2013.01); G02B 6/4249 (2013.01); G02B 6/4271 (2013.01); G02B 6/4295 (2013.01); H01S 5/423 (2013.01);
Abstract

A package structure includes a circuit board, a package substrate, a fine metal L/S RDL-substrate, an electronic assembly, a photonic assembly, a heat dissipation assembly, and an optical fiber assembly. The package substrate is disposed on and electrically connected to the circuit board. The fine metal L/S RDL-substrate is disposed on and electrically connected to the package substrate. The electronic assembly includes an application specific integrated circuit (ASIC) assembly, an electronic integrated circuit (EIC) assembly, and a photonic integrated circuit (PIC) assembly which are respectively disposed on the fine metal L/S RDL-substrate and electrically connected to the package substrate by the fine metal L/S RDL-substrate. The heat dissipation assembly is disposed on the electronic assembly. The optical fiber assembly is disposed on the package substrate and electrically connected to the package substrate and the PIC assembly. A packaging method of the VCSEL array chip is presented.


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