The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 26, 2023

Filed:

May. 23, 2022
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;

Inventors:

Hsin-Wen Su, Yunlin County, TW;

Chia-En Huang, Hsinchu County, TW;

Shih-Hao Lin, Hsinchu, TW;

Lien-Jung Hung, Taipei, TW;

Ping-Wei Wang, Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10B 41/30 (2023.01); H01L 23/522 (2006.01); G11C 7/18 (2006.01); H01L 29/872 (2006.01); G11C 8/14 (2006.01); H10B 43/30 (2023.01);
U.S. Cl.
CPC ...
H10B 41/30 (2023.02); G11C 7/18 (2013.01); G11C 8/14 (2013.01); H01L 23/5226 (2013.01); H01L 29/872 (2013.01); H10B 43/30 (2023.02);
Abstract

A memory device includes a substrate, a first transistor and a second transistor, a Schottky diode, a first word line, a second word line, and a bit line. The first transistor and the second transistor are over the substrate, wherein a first source/drain structure of the first transistor is electrically connected to a first source/drain structure of the second transistor. The Schottky diode is electrically connected to a gate structure of the first transistor. The first word line is electrically connected to the gate structure of the first transistor through the Schottky diode. The second word line is electrically connected to a gate structure of the second transistor. The bit line is electrically connected to a second source/drain structure of the second transistor.


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