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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 11855217 B1

PDFFull Text
Date of Patent:
Dec. 26, 2023

Filed:

Dec. 14, 2020

Semiconductor device having a conductive contact in direct contact with an upper surface and a sidewall of a gate metal layer

Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;

Inventors:

Che-Cheng Chang, New Taipei, TW;

Chih-Han Lin, Hsinchu, TW;

Horng-Huei Tseng, Hsinchu, TW;

Assignee:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu, TW;

Attorney:

Slater Matsil, LLP

Primary Examiner:

Younes Boulghassoul

Int. Cl.
CPC ...
H01L 29/78 (2006.01); H01L 23/535 (2006.01); H01L 29/423 (2006.01); H01L 29/49 (2006.01); H01L 21/28 (2006.01); H01L 21/3065 (2006.01); H01L 21/308 (2006.01); H01L 21/762 (2006.01); H01L 21/768 (2006.01); H01L 29/66 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7851 (2013.01); H01L 21/28008 (2013.01); H01L 21/3065 (2013.01); H01L 21/3081 (2013.01); H01L 21/76224 (2013.01); H01L 21/76802 (2013.01); H01L 21/76877 (2013.01); H01L 23/535 (2013.01); H01L 29/42376 (2013.01); H01L 29/4991 (2013.01); H01L 29/66795 (2013.01); H01L 29/785 (2013.01);
Abstract

A representative method for manufacturing a semiconductor device (e.g., a fin field-effect transistor) includes the steps of forming a gate structure having a first lateral width, and forming a first via opening over the gate structure. The first via opening has a lowermost portion that exposes an uppermost surface of the gate structure. The lowermost portion of the first via opening has a second lateral width. A ratio of the second lateral width to the first lateral width is less than about 1.1. A source/drain (S/D) region is disposed laterally adjacent the gate structure. A contact feature is disposed over the S/D region. A second via opening extends to and exposes an uppermost surface of the contact feature. A bottommost portion of the second via opening is disposed above a topmost portion of the gate structure.

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