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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 11855208 B1

PDFFull Text
Date of Patent:
Dec. 26, 2023

Filed:

Jun. 11, 2020

Method for forming fin field effect transistor (finfet) device structure

Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;

Inventors:

Chun-Hsiung Tsai, Xinpu Township, Hsinchu County, TW;

Shahaji B. More, Hsinchu, TW;

Cheng-Yi Peng, Taipei, TW;

Yu-Ming Lin, Hsinchu, TW;

Kuo-Feng Yu, Zhudong Township, Hsinchu County, TW;

Ziwei Fang, Hsinchu, TW;

Assignee:

TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., Hsinchu, TW;

Attorney:

Birch, Stewart, Kolasch & Birch, LLP

Primary Examiner:

Benjamin Tzu-Hung Liu

Int. Cl.
CPC ...
H01L 29/78 (2006.01); H01L 21/02 (2006.01); H01L 21/265 (2006.01); H01L 21/3065 (2006.01); H01L 21/8234 (2006.01); H01L 27/088 (2006.01); H01L 29/06 (2006.01); H01L 29/08 (2006.01); H01L 29/167 (2006.01); H01L 29/45 (2006.01); H01L 29/66 (2006.01); H01L 21/027 (2006.01); H01L 29/161 (2006.01); H01L 29/36 (2006.01); H01L 29/165 (2006.01); H01L 21/3105 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7848 (2013.01); H01L 21/02532 (2013.01); H01L 21/26513 (2013.01); H01L 21/3065 (2013.01); H01L 21/823418 (2013.01); H01L 21/823431 (2013.01); H01L 21/823437 (2013.01); H01L 27/0886 (2013.01); H01L 29/0649 (2013.01); H01L 29/0847 (2013.01); H01L 29/165 (2013.01); H01L 29/167 (2013.01); H01L 29/45 (2013.01); H01L 29/665 (2013.01); H01L 29/6656 (2013.01); H01L 29/66545 (2013.01); H01L 29/66636 (2013.01); H01L 29/66795 (2013.01); H01L 29/785 (2013.01); H01L 29/7851 (2013.01); H01L 21/0274 (2013.01); H01L 21/31053 (2013.01); H01L 29/161 (2013.01); H01L 29/36 (2013.01);
Abstract

A method for forming a FinFET device structure is provided. The method includes forming a fin structure extended above a substrate and forming a gate structure formed over a portion of the fin structure. The method also includes forming a source/drain (S/D) structure over the fin structure, and the S/D structure is adjacent to the gate structure. The method further includes doping an outer portion of the S/D structure to form a doped region, and the doped region includes gallium (Ga). The method includes forming a metal silicide layer over the doped region; and forming an S/D contact structure over the metal silicide layer.

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