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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 11855175 B1

PDFFull Text
Date of Patent:
Dec. 26, 2023

Filed:

Jul. 20, 2022

Fabrication of long gate devices

Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;

Inventors:

Sung-Hsin Yang, Hsinchu, TW;

Jung-Chi Jeng, Tainan, TW;

Ru-Shang Hsiao, Hsinchu, TW;

Assignee:

TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., Hsinchu, TW;

Attorney:

HAYNES AND BOONE, LLP

Primary Examiner:

Cheung Lee

Int. Cl.
CPC ...
H01L 29/66 (2006.01); H01L 21/8234 (2006.01); H01L 27/088 (2006.01); H01L 21/3213 (2006.01); H01L 21/8238 (2006.01); H01L 29/78 (2006.01);
U.S. Cl.
CPC ...
H01L 29/66484 (2013.01); H01L 21/32139 (2013.01); H01L 21/82385 (2013.01); H01L 21/823431 (2013.01); H01L 21/823437 (2013.01); H01L 21/823456 (2013.01); H01L 21/823821 (2013.01); H01L 27/0886 (2013.01); H01L 29/66545 (2013.01); H01L 29/7855 (2013.01);
Abstract

Semiconductor devices and methods of forming the same are provided. An example method includes providing a workpiece including a first dummy gate stack and a second dummy gate stack in a first area of the workpiece, a third dummy gate stack and a fourth dummy gate stack in a second area of the workpiece, a hard mask layer over each of the first dummy gate stack, the second dummy gate stack, the third dummy gate stack, and the fourth dummy gate stack. The method further includes depositing a photoresist (PR) layer over the workpiece to form a first PR layer portion over the first area and a second PR layer portion over the second area; and selectively forming a first opening through the second PR layer portion over the third dummy gate stack and a second opening through the second PR layer portion over the fourth dummy gate stack.

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