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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 11855146 B1

PDFFull Text
Date of Patent:
Dec. 26, 2023

Filed:

Jan. 17, 2022

Melt anneal source and drain regions

Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;

Inventors:

Su-Hao Liu, Jhongpu Township, TW;

Wen-Yen Chen, Hsinchu, TW;

Li-Heng Chen, Taichung, TW;

Li-Ting Wang, Hsinchu, TW;

Liang-Yin Chen, Hsinchu, TW;

Huicheng Chang, Tainan, TW;

Yee-Chia Yeo, Hsinchu, TW;

Ying-Lang Wang, Tien-Chung Village, TW;

Assignee:

TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu, TW;

Attorney:

Slater Matsil, LLP

Primary Examiner:

Marcos D Pizarro

Int. Cl.
CPC ...
H01L 29/08 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01); H01L 29/161 (2006.01); H01L 27/092 (2006.01); H01L 21/8238 (2006.01); H01L 21/02 (2006.01); H01L 21/265 (2006.01); H01L 21/285 (2006.01); H01L 21/768 (2006.01); H01L 21/8234 (2006.01); H01L 21/324 (2006.01);
U.S. Cl.
CPC ...
H01L 29/0847 (2013.01); H01L 21/02532 (2013.01); H01L 21/26506 (2013.01); H01L 21/28518 (2013.01); H01L 21/324 (2013.01); H01L 21/76814 (2013.01); H01L 21/823418 (2013.01); H01L 21/823431 (2013.01); H01L 21/823814 (2013.01); H01L 21/823821 (2013.01); H01L 21/823828 (2013.01); H01L 27/0924 (2013.01); H01L 29/161 (2013.01); H01L 29/66507 (2013.01); H01L 29/66545 (2013.01); H01L 29/66795 (2013.01); H01L 29/785 (2013.01); H01L 29/7845 (2013.01); H01L 29/7848 (2013.01); H01L 29/7851 (2013.01); H01L 2029/7858 (2013.01);
Abstract

A method includes forming a gate stack on a first portion of a semiconductor substrate, removing a second portion of the semiconductor substrate on a side of the gate stack to form a recess, growing a semiconductor region starting from the recess, implanting the semiconductor region with an impurity, and performing a melt anneal on the semiconductor region. At least a portion of the semiconductor region is molten during the melt anneal.

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