The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 26, 2023

Filed:

Aug. 27, 2021
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Guan-Lin Chen, Hsinchu, TW;

Kuo-Cheng Chiang, Hsinchu, TW;

Shi Ning Ju, Hsinchu, TW;

Jung-Chien Cheng, Hsinchu, TW;

Chih-Hao Wang, Hsinchu, TW;

Kuan-Lun Cheng, Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/088 (2006.01); H01L 21/8234 (2006.01);
U.S. Cl.
CPC ...
H01L 27/088 (2013.01); H01L 21/823456 (2013.01); H01L 21/823475 (2013.01); H01L 21/823481 (2013.01); H01L 21/823412 (2013.01);
Abstract

A semiconductor device structure, along with methods of forming such, are described. The structure includes a dielectric feature comprising a first dielectric layer and a second dielectric layer, the first dielectric layer has a first sidewall and a second sidewall opposing the first sidewall, and the second dielectric layer is in contact with at least a portion of the first sidewall and at least a portion of the second sidewall. The structure also includes a first semiconductor layer adjacent the first sidewall, wherein the first semiconductor layer is in contact with the second dielectric layer. The structure further includes a first gate electrode layer surrounding at least three surfaces of the first semiconductor layer, wherein the first gate electrode layer has a surface facing the second dielectric layer, and the surface extends over a plane defined by an interface between the second dielectric layer and the first semiconductor layer.


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