The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 26, 2023

Filed:

Dec. 19, 2019
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Zhimin Wan, Chandler, AZ (US);

Chia-Pin Chiu, Tempe, AZ (US);

Peng Li, Chandler, AZ (US);

Shankar Devasenathipathy, Tempe, AZ (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/367 (2006.01); H01L 25/065 (2023.01); H01L 23/42 (2006.01); H01L 23/373 (2006.01); H01L 23/538 (2006.01); H01L 25/00 (2006.01); H01L 21/56 (2006.01); H01L 21/48 (2006.01); H01L 23/00 (2006.01);
U.S. Cl.
CPC ...
H01L 23/367 (2013.01); H01L 21/4853 (2013.01); H01L 21/56 (2013.01); H01L 23/3736 (2013.01); H01L 23/42 (2013.01); H01L 23/5386 (2013.01); H01L 24/32 (2013.01); H01L 25/0652 (2013.01); H01L 25/50 (2013.01); H01L 2224/32225 (2013.01); H01L 2225/06589 (2013.01);
Abstract

Embodiments include semiconductor packages and a method to form such packages. A semiconductor package includes first and second bottom dies on a package substrate. The semiconductor package includes first top dies on the first bottom die, second top dies on the second bottom die, and a pedestal on the first and second bottom dies. The pedestal comprises a high thermal conductive material and is positioned on a region of top surfaces of the first and second bottom dies. The semiconductor package includes an encapsulation layer over the first and second bottom dies, and surrounds the first and second top dies and the pedestal. The semiconductor package includes a TIM over the first and second top dies, pedestal, and encapsulation layer, and an integrated heat spreader (IHS) over the TIM. The pedestal is on a periphery region of the top surfaces of the first and second bottom dies.


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