The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 26, 2023
Filed:
Jul. 25, 2022
Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;
Jin-Aun Ng, Hsinchu, TW;
Kuo-Cheng Chiang, Zhubei, TW;
Carlos H. Diaz, Los Altos Hills, CA (US);
Jean-Pierre Colinge, Belgium, FR;
Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;
Abstract
Among other things, one or semiconductor arrangements, and techniques for forming such semiconductor arrangements are provided. For example, one or more silicon and silicon germanium stacks are utilized to form PMOS transistors comprising germanium nanostructure channels and NMOS transistors comprising silicon nanostructure channels. In an example, a first silicon and silicon germanium stack is oxidized to transform silicon to silicon oxide regions, which are removed to form germanium nanostructure channels for PMOS transistors. In another example, silicon and germanium layers within a second silicon and silicon germanium stack are removed to form silicon nanostructure channels for NMOS transistors. PMOS transistors having germanium nanostructure channels and NMOS transistors having silicon nanostructure channels are formed as part of a single fabrication process.