The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 26, 2023

Filed:

Jun. 22, 2020
Applicant:

Applied Materials, Inc., Santa Clara, CA (US);

Inventors:

Jungrae Park, Santa Clara, CA (US);

Zavier Zai Yeong Tan, Singapore, SG;

Karthik Balakrishnan, Singapore, SG;

James S. Papanu, San Rafael, CA (US);

Wei-Sheng Lei, San Jose, CA (US);

Assignee:

Applied Materials, Inc., Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/78 (2006.01); H01L 21/67 (2006.01); H01L 21/02 (2006.01); H01L 21/268 (2006.01); H01L 21/3065 (2006.01);
U.S. Cl.
CPC ...
H01L 21/78 (2013.01); H01L 21/67069 (2013.01); H01L 21/67115 (2013.01); H01L 21/02071 (2013.01); H01L 21/268 (2013.01); H01L 21/3065 (2013.01);
Abstract

An embodiment disclosed herein includes a method of dicing a wafer comprising a plurality of integrated circuits. In an embodiment, the method comprises forming a mask above the semiconductor wafer, and patterning the mask and the semiconductor wafer with a first laser process. The method may further comprise patterning the mask and the semiconductor wafer with a second laser process, where the second laser process is different than the first laser process. In an embodiment, the method may further comprise etching the semiconductor wafer with a plasma etching process to singulate the integrated circuits.


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