The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 26, 2023

Filed:

Aug. 30, 2021
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Chun-Cheng Chou, Taichung, TW;

Yu-Fang Huang, Hsinchu, TW;

Kuo-Ju Chen, Taichung, TW;

Ying-Liang Chuang, Zhubei, TW;

Chun-Neng Lin, Hsinchu, TW;

Ming-Hsi Yeh, Hsinchu, TW;

Kuo-Bin Huang, Jhubei, TW;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/768 (2006.01); H01L 23/522 (2006.01); H01L 23/532 (2006.01); H01L 21/3215 (2006.01);
U.S. Cl.
CPC ...
H01L 21/76805 (2013.01); H01L 21/7685 (2013.01); H01L 21/76867 (2013.01); H01L 23/5226 (2013.01); H01L 21/3215 (2013.01); H01L 23/53257 (2013.01);
Abstract

A method for making a middle-of-line interconnect structure in a semiconductor device includes forming, near a surface of a first interconnect structure comprised of a first metal, a region of varied composition including the first metal and a second element. The method further includes forming a recess within the region of varied composition. The recess laterally extends a first distance along the surface and vertically extends a second distance below the first surface. The method further includes filling the recess with a second metal to form a second interconnect structure that contacts the first interconnect structure.


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