The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 19, 2023

Filed:

Dec. 13, 2018
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Dae-Woo Kim, Phoenix, AZ (US);

Sujit Sharan, Chandler, AZ (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/498 (2006.01); H01L 23/538 (2006.01); H01L 23/13 (2006.01); H01L 25/065 (2023.01); H01L 23/00 (2006.01); H01L 23/48 (2006.01);
U.S. Cl.
CPC ...
H01L 23/49827 (2013.01); H01L 23/13 (2013.01); H01L 23/49822 (2013.01); H01L 23/5381 (2013.01); H01L 24/00 (2013.01); H01L 25/0655 (2013.01); H01L 23/48 (2013.01); H01L 24/16 (2013.01); H01L 24/17 (2013.01); H01L 2224/14 (2013.01); H01L 2224/16225 (2013.01); H01L 2224/16238 (2013.01); H01L 2224/171 (2013.01); H01L 2224/1703 (2013.01); H01L 2224/17133 (2013.01); H01L 2224/17177 (2013.01); H01L 2924/1431 (2013.01); H01L 2924/1435 (2013.01); H01L 2924/153 (2013.01); H01L 2924/1517 (2013.01);
Abstract

Alternative surfaces for conductive pad layers of silicon bridges for semiconductor packages, and the resulting silicon bridges and semiconductor packages, are described. In an example, a semiconductor structure includes a substrate having a lower insulating layer disposed thereon. The substrate has a perimeter. A metallization structure is disposed on the lower insulating layer. The metallization structure includes conductive routing disposed in a dielectric material stack. First and second pluralities of conductive pads are disposed in a plane above the metallization structure. Conductive routing of the metallization structure electrically connects the first plurality of conductive pads with the second plurality of conductive pads. An upper insulating layer is disposed on the first and second pluralities of conductive pads. The upper insulating layer has a perimeter substantially the same as the perimeter of the substrate.


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