The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 12, 2023
Filed:
Jun. 30, 2022
Applicant:
Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu, TW;
Inventors:
Assignee:
Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 16/00 (2006.01); H10B 41/35 (2023.01); H01L 29/66 (2006.01); H01L 29/06 (2006.01); H01L 29/788 (2006.01); G11C 16/10 (2006.01); H10B 41/41 (2023.01); H10B 41/42 (2023.01); G11C 16/30 (2006.01);
U.S. Cl.
CPC ...
H10B 41/35 (2023.02); G11C 16/10 (2013.01); H01L 29/0649 (2013.01); H01L 29/66825 (2013.01); H01L 29/7883 (2013.01); H10B 41/41 (2023.02); H10B 41/42 (2023.02); G11C 16/30 (2013.01);
Abstract
Various embodiments of the present disclosure are directed towards an integrated chip including a first well region and a second well region disposed within a substrate. A gate electrode overlies the first well region and the second well region. A first memory active region is disposed within the second well region. A second memory active region is disposed within the second well region and is laterally offset from the first memory active region by a non-zero distance.