The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 12, 2023

Filed:

May. 09, 2022
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsin-Chu, TW;

Inventors:

Chang-Yin Chen, Taipei, TW;

Che-Cheng Chang, New Taipei, TW;

Chih-Han Lin, Hsinchu, TW;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/49 (2006.01); H01L 29/423 (2006.01); H01L 21/8238 (2006.01); H01L 29/66 (2006.01); H01L 29/51 (2006.01); H01L 21/308 (2006.01); H01L 27/092 (2006.01); H01L 29/10 (2006.01); H01L 21/306 (2006.01); H01L 21/3065 (2006.01);
U.S. Cl.
CPC ...
H01L 21/82385 (2013.01); H01L 21/3065 (2013.01); H01L 21/3086 (2013.01); H01L 21/30608 (2013.01); H01L 21/823814 (2013.01); H01L 21/823821 (2013.01); H01L 27/0924 (2013.01); H01L 29/1033 (2013.01); H01L 29/42376 (2013.01); H01L 29/4966 (2013.01); H01L 29/517 (2013.01); H01L 29/66545 (2013.01); H01L 29/66553 (2013.01); H01L 29/66795 (2013.01);
Abstract

A method includes providing a substrate having a channel region, forming a gate stack layer over the channel region, forming a patterned hard mask over the gate stack layer, etching a top portion of the gate stack layer through openings in the patterned hard mask with a first etchant, etching a middle portion and a bottom portion of the gate stack layer with a second etchant that includes a passivating gas. A gate stack is formed with a passivation layer deposited on sidewalls of the gate stack. The method also includes etching the gate stack with a third etchant, thereby removing a bottom portion of the passivation layer and recessing a bottom portion of the gate stack.


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