The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 05, 2023
Filed:
Dec. 17, 2021
Globalfoundries U.s. Inc., Malta, NY (US);
Tom Herrmann, Dresden, DE;
Zhixing Zhao, Dresden, DE;
Alban Zaka, Dresden, DE;
Yiching Chen, San Jose, CA (US);
GlobalFoundries U.S. Inc., Malta, NY (US);
Abstract
A structure including a semiconductor-on-insulator (SOI) substrate. The SOI substrate includes an SOI layer over a buried insulator layer over a base semiconductor layer. The structure includes a high-voltage first field effect transistor (FET) adjacent to a high performance, low voltage second FET. The high voltage FET has a gate electrode on the buried insulator layer, and a source and a drain in the base semiconductor layer under the buried insulator layer. Hence, the buried insulator layer operates as a gate dielectric for the high voltage FET. The low voltage FET has a source and a drain over the buried insulator layer, i.e., in the SOI layer. A trench isolation is in each of the source and the drain of the first, high voltage FET. The source of the high voltage FET surrounds the trench isolation therein.