The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 05, 2023

Filed:

Dec. 27, 2019
Applicant:

Taiwan Semiconductor Manufacturing Company Ltd., Hsinchu, TW;

Inventors:

Cheng-Ying Ho, Chiayi County, TW;

Wen-De Wang, Chiayi County, TW;

Jen-Cheng Liu, Hsin-Chu, TW;

Dun-Nian Yaung, Taipei, TW;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/762 (2006.01); H01L 25/00 (2006.01); H01L 23/522 (2006.01); H01L 21/768 (2006.01); H01L 25/065 (2023.01); H01L 23/00 (2006.01); H01L 23/48 (2006.01); H01L 21/285 (2006.01); H01L 21/288 (2006.01); H01L 23/532 (2006.01);
U.S. Cl.
CPC ...
H01L 25/50 (2013.01); H01L 21/2855 (2013.01); H01L 21/2885 (2013.01); H01L 21/76251 (2013.01); H01L 21/76898 (2013.01); H01L 23/481 (2013.01); H01L 23/5226 (2013.01); H01L 24/82 (2013.01); H01L 24/83 (2013.01); H01L 24/92 (2013.01); H01L 25/0657 (2013.01); H01L 21/76805 (2013.01); H01L 23/53214 (2013.01); H01L 23/53228 (2013.01); H01L 23/53242 (2013.01); H01L 23/53257 (2013.01); H01L 24/80 (2013.01); H01L 2224/08145 (2013.01); H01L 2224/245 (2013.01); H01L 2224/24145 (2013.01); H01L 2224/80895 (2013.01); H01L 2224/80896 (2013.01); H01L 2224/82106 (2013.01); H01L 2224/83894 (2013.01); H01L 2224/9202 (2013.01); H01L 2224/9212 (2013.01); H01L 2225/06524 (2013.01); H01L 2225/06544 (2013.01); H01L 2225/06565 (2013.01);
Abstract

A semiconductor device structure includes a first chip, second chip, a first metal structure, a second metal structure, a first via structure and a second via structure. The first chip includes n inter metal dielectric (IMD) layer, which includes different materials adjacent to generate a number of staggered portions having a zigzag configuration. The second chip bonded to the first chip generates a bonding interface. The first metal structure is disposed in the first chip and between the staggered portions and the bonding interface. The first via structure in the first chip stops at the first metal structure. The first via structure includes a first via metal and a first via dielectric layer. A surface roughness of the staggered portions is substantially greater than a surface roughness of the first via dielectric layer. The second via structure extends from the first via structure to the second metal structure.


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