The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 05, 2023

Filed:

May. 12, 2022
Applicants:

Stmicroelectronics S.r.l., Agrate Brianza, IT;

Stmicroelectronics International N.v., Geneva, CH;

Inventors:

Nitin Chawla, Noida, IN;

Giuseppe Desoli, San Fermo Della Battaglia, IT;

Anuj Grover, New Delhi, IN;

Thomas Boesch, Rovio, CH;

Surinder Pal Singh, Noida, IN;

Manuj Ayodhyawasi, Noida, IN;

Assignees:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 3/06 (2006.01); G06N 3/08 (2023.01);
U.S. Cl.
CPC ...
G06F 3/0604 (2013.01); G06F 3/0619 (2013.01); G06F 3/0655 (2013.01); G06F 3/0679 (2013.01); G06N 3/08 (2013.01);
Abstract

A memory array arranged as a plurality of memory cells. The memory cells are configured to operate at a determined voltage. A memory management circuitry coupled to the plurality of memory cells tags a first set of the plurality of memory cells as low-voltage cells and tags a second set of the plurality of memory cells as high-voltage cells. A power source provides a low voltage to the first set of memory cells and provides a high voltage to the second set of memory cells based on the tags.


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