The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 28, 2023

Filed:

Jun. 10, 2022
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;

Inventors:

Yu-Chu Lin, Tainan, TW;

Chi-Chung Jen, Kaohsiung, TW;

Yen-Di Wang, Taipei, TW;

Jia-Yang Ko, Kaohsiung, TW;

Men-Hsi Tsai, Tainan, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/00 (2006.01); H01L 29/423 (2006.01); H01L 29/788 (2006.01); H01L 21/28 (2006.01); H01L 29/66 (2006.01); H10B 41/10 (2023.01); H10B 41/30 (2023.01);
U.S. Cl.
CPC ...
H01L 29/42324 (2013.01); H01L 29/4011 (2019.08); H01L 29/66825 (2013.01); H01L 29/788 (2013.01); H10B 41/10 (2023.02); H10B 41/30 (2023.02);
Abstract

A memory device is provided. The memory device includes a semiconductor substrate, a tunneling layer, a floating gate electrode, a dielectric layer, and a control gate electrode. The semiconductor substrate has an active region. The tunneling layer is over the active region of the semiconductor substrate. The floating gate electrode is over the tunneling layer. The floating gate electrode has a first portion and a second portion electrically connected to the first portion. The dielectric layer is over the floating gate electrode. The control gate electrode is over the dielectric layer. The control gate electrode has a first portion interposed between the first and second portions of the floating gate electrode.


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