The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 28, 2023

Filed:

Dec. 16, 2021
Applicant:

Mediatek Inc., Hsin-Chu, TW;

Inventors:

Yao-Chun Su, Hsinchu, TW;

Chih-Jung Hsu, Hsinchu, TW;

Yi-Jou Lin, Hsinchu, TW;

I-Hsuan Peng, Hsinchu, TW;

Assignee:

MEDIATEK INC., Hsin-Chu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/538 (2006.01); H01L 23/31 (2006.01); H01L 23/367 (2006.01); H01L 23/00 (2006.01); H01L 23/58 (2006.01); H01L 23/66 (2006.01); H01L 25/065 (2023.01);
U.S. Cl.
CPC ...
H01L 23/5386 (2013.01); H01L 23/3128 (2013.01); H01L 23/3675 (2013.01); H01L 23/5385 (2013.01); H01L 23/562 (2013.01); H01L 23/585 (2013.01); H01L 23/66 (2013.01); H01L 25/0655 (2013.01); H01L 2223/6638 (2013.01); H01L 2223/6666 (2013.01);
Abstract

An electronic package includes a package substrate of a rectangular shape, and a chip package including a first interface circuit die and a second interface circuit die. The first interface circuit die and second interface circuit die are mounted on a redistribution layer structure and encapsulated within a molding compound. The chip package is mounted on a top surface of the package substrate and rotated relative to the package substrate above a vertical axis that is orthogonal to the top surface through a rotation offset angle. A metal ring is mounted on the top surface of the package substrate.


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