The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 21, 2023

Filed:

Aug. 19, 2021
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu, TW;

Inventors:

Yi-Huan Chen, Hsin Chu, TW;

Chien-Chih Chou, New Taipei, TW;

Ta-Wei Lin, Minxiong Township, TW;

Hsiao-Chin Tuan, Taowan, TW;

Alexander Kalnitsky, San Francisco, CA (US);

Kong-Beng Thei, Pao-Shan Village, TW;

Chia-Hong Wu, Taichung, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/8238 (2006.01); H01L 29/423 (2006.01); H01L 29/66 (2006.01); H01L 29/51 (2006.01); H01L 29/49 (2006.01); H01L 21/3105 (2006.01); H01L 29/08 (2006.01); H01L 21/3213 (2006.01); H01L 27/092 (2006.01); H01L 21/28 (2006.01); H01L 29/45 (2006.01);
U.S. Cl.
CPC ...
H01L 21/823835 (2013.01); H01L 21/28088 (2013.01); H01L 21/31053 (2013.01); H01L 21/32133 (2013.01); H01L 21/32139 (2013.01); H01L 21/823814 (2013.01); H01L 21/823871 (2013.01); H01L 27/092 (2013.01); H01L 29/0847 (2013.01); H01L 29/42372 (2013.01); H01L 29/45 (2013.01); H01L 29/4966 (2013.01); H01L 29/513 (2013.01); H01L 29/665 (2013.01); H01L 29/66515 (2013.01); H01L 29/42364 (2013.01); H01L 29/517 (2013.01);
Abstract

Various embodiments of the present disclosure are directed towards an integrated chip including a gate dielectric structure over a substrate. A metal layer overlies the gate dielectric structure. A conductive layer overlies the metal layer. A polysilicon layer contacts opposing sides of the conductive layer. A bottom surface of the polysilicon layer is aligned with a bottom surface of the conductive layer. A dielectric layer overlies the polysilicon layer. The dielectric layer continuously extends from sidewalls of the polysilicon layer to an upper surface of the conductive layer.


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