The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 14, 2023

Filed:

Dec. 08, 2020
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Wilfred Gomes, Portland, OR (US);

Abhishek A. Sharma, Hillsboro, OR (US);

Mauro J. Kobrinsky, Portland, OR (US);

Doug B. Ingerly, Portland, OR (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 25/18 (2023.01); H01L 23/528 (2006.01); H01L 23/522 (2006.01); H01L 23/00 (2006.01); H01L 23/532 (2006.01);
U.S. Cl.
CPC ...
H01L 25/18 (2013.01); H01L 23/5226 (2013.01); H01L 23/5283 (2013.01); H01L 24/08 (2013.01); H01L 24/16 (2013.01); H01L 24/32 (2013.01); H01L 23/53223 (2013.01); H01L 23/53238 (2013.01); H01L 23/53266 (2013.01); H01L 2224/08145 (2013.01); H01L 2224/08501 (2013.01); H01L 2224/16145 (2013.01); H01L 2224/32145 (2013.01); H01L 2224/32501 (2013.01); H01L 2924/01006 (2013.01); H01L 2924/01007 (2013.01); H01L 2924/01014 (2013.01);
Abstract

Microelectronic assemblies fabricated using hybrid manufacturing, as well as related devices and methods, are disclosed herein. As used herein, 'hybrid manufacturing' refers to fabricating a microelectronic assembly by arranging together at least two IC structures fabricated by different manufacturers, using different materials, or different manufacturing techniques. For example, a microelectronic assembly may include a first IC structure that includes first interconnects and a second IC structure that includes second interconnects, where at least some of the first and second interconnects may include a liner and an electrically conductive fill material, and where a material composition of the liner/electrically conductive fill material of the first interconnects may be different from a material composition of the liner/electrically conductive fill material of the second interconnects.


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