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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 11812670 B1

PDFFull Text
Date of Patent:
Nov. 07, 2023

Filed:

Nov. 03, 2022

Memory device comprising a top via electrode and methods of making such a memory device

Applicant:

Globalfoundries U.s. Inc., Malta, NY (US);

Inventors:

Yanping Shen, Saratoga Springs, NY (US);

Haiting Wang, Clifton Park, NY (US);

Sipeng Gu, Clifton Park, NY (US);

Assignee:

GlobalFoundries U.S. Inc., Malta, NY (US);

Attorneys:

Anthony Canale

Hoffman Warnick LLC

Primary Examiner:

Amar Movva

Int. Cl.
CPC ...
H10N 50/80 (2023.01); H10B 51/30 (2023.01); H10B 61/00 (2023.01); H10B 63/00 (2023.01); H10N 50/01 (2023.01); H10N 50/10 (2023.01); H10N 50/85 (2023.01); H10N 70/00 (2023.01); H10N 70/20 (2023.01);
U.S. Cl.
CPC ...
H10N 50/80 (2023.02); H10B 51/30 (2023.02); H10B 61/00 (2023.02); H10B 63/00 (2023.02); H10N 50/01 (2023.02); H10N 50/10 (2023.02); H10N 50/85 (2023.02); H10N 70/011 (2023.02); H10N 70/231 (2023.02); H10N 70/826 (2023.02); H10N 70/841 (2023.02); H10N 70/881 (2023.02);
Abstract

An illustrative device disclosed herein includes at least one layer of insulating material, a conductive contact structure having a conductive line portion and a conductive via portion and a memory cell positioned in a first opening in the at least one layer of insulating material. In this illustrative example, the memory cell includes a bottom electrode, a memory state material positioned above the bottom electrode and an internal sidewall spacer positioned within the first opening and above at least a portion of the memory state material, wherein the internal sidewall spacer defines a spacer opening and wherein the conductive via portion is positioned within the spacer opening and above a portion of the memory state material.

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