The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 07, 2023

Filed:

May. 10, 2021
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Tsun-Kai Tsao, Tainan, TW;

Hung-Ling Shih, Tainan, TW;

Po-Wei Liu, Tainan, TW;

Shun-Shing Yang, Tainan, TW;

Wen-Tuo Huang, Tainan, TW;

Yong-Shiuan Tsair, Tainan, TW;

ShihKuang Yang, Tainan, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10B 41/41 (2023.01); H01L 21/28 (2006.01); H01L 29/423 (2006.01); H10B 41/30 (2023.01); H01L 21/3105 (2006.01);
U.S. Cl.
CPC ...
H10B 41/41 (2023.02); H01L 21/31056 (2013.01); H01L 29/40114 (2019.08); H01L 29/42328 (2013.01); H10B 41/30 (2023.02);
Abstract

A semiconductor device includes a non-volatile memory and a logic circuit. The non-volatile memory includes a stacked structure comprising a first insulating layer, a floating gate, a second insulating layer, a control gate and a third insulating layer stacked in this order from a substrate; an erase gate line; and a word line. The logic circuit includes a field effect transistor comprising a gate electrode. The word line includes a protrusion, and a height of the protrusion from the substrate is higher than a height of the erase gate line from the substrate. The word line and the gate electrode are formed of polysilicon.


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