The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 07, 2023

Filed:

Mar. 31, 2021
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;

Inventors:

Shiang-Bau Wang, Pingzchen, TW;

Ryan Chia-Jen Chen, Hsinchu, TW;

Shu-Yuan Ku, Zhubei, TW;

Ming-Ching Chang, Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/02 (2006.01); H01L 29/423 (2006.01); H01L 29/49 (2006.01); H01L 21/8234 (2006.01); H01L 21/311 (2006.01); H01L 21/762 (2006.01); H01L 27/088 (2006.01); H01L 21/3105 (2006.01); H01L 21/3213 (2006.01); H01L 29/06 (2006.01); H01L 21/027 (2006.01); H01L 29/66 (2006.01); H01L 21/285 (2006.01);
U.S. Cl.
CPC ...
H01L 27/0207 (2013.01); H01L 21/31053 (2013.01); H01L 21/31111 (2013.01); H01L 21/32139 (2013.01); H01L 21/76224 (2013.01); H01L 21/823431 (2013.01); H01L 21/823437 (2013.01); H01L 21/823481 (2013.01); H01L 27/0886 (2013.01); H01L 29/0649 (2013.01); H01L 29/42372 (2013.01); H01L 29/4958 (2013.01); H01L 29/4966 (2013.01); H01L 21/0276 (2013.01); H01L 21/28556 (2013.01); H01L 21/823418 (2013.01); H01L 27/088 (2013.01); H01L 29/6656 (2013.01); H01L 29/66545 (2013.01); H01L 29/66636 (2013.01);
Abstract

Methods for cutting (e.g., dividing) metal gate structures in semiconductor device structures are provided. A dual layer structure can form sub-metal gate structures in a replacement gate manufacturing processes, in some examples. In an example, a semiconductor device includes a plurality of metal gate structures disposed in an interlayer dielectric (ILD) layer disposed on a substrate, an isolation structure disposed between the metal gate structures, wherein the ILD layer circumscribes a perimeter of the isolation structure, and a dielectric structure disposed between the ILD layer and the isolation structure.


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