The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 31, 2023

Filed:

Jan. 28, 2021
Applicant:

Globalfoundries U.s. Inc., Santa Clara, CA (US);

Inventors:

Saquib B. Halim, Bavaria, DE;

Frank G. Kuechenmeister, Dresden, DE;

Kashi V Machani, Dresden, DE;

Christian Goetze, Dresden, DE;

Assignee:

GLOBALFOUNDRIES U.S. Inc., Santa Clara, CA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/538 (2006.01); H01L 23/00 (2006.01);
U.S. Cl.
CPC ...
H01L 23/5384 (2013.01); H01L 23/5383 (2013.01); H01L 23/5386 (2013.01); H01L 24/14 (2013.01);
Abstract

Disclosed are chip module structures, each having a robust in-package interconnect for reliable performance. Some of the chip module structures achieve interconnect robustness through the use of vias in a spiral step pattern within the interconnect itself. Some chip module structures achieve interconnect robustness through the use of an interconnect stabilizer (referred to herein as a stabilization structure, fence or cage)), which includes vias in a repeating step pattern encircling the in-package interconnect, which is electrically isolated from back side solder balls, front side collapse chip connections (referred to herein as C4 connections), and the interconnect itself, and which is optionally connected to ground. Some chip module structures achieve interconnect robustness through the use of a combination of both vias in a spiral step pattern within the interconnect itself and an interconnect stabilizer.


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