The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 24, 2023

Filed:

Feb. 12, 2021
Applicant:

Yangtze Memory Technologies Co., Ltd., Hubei, CN;

Inventors:

Li Hong Xiao, Hubei, CN;

Zongliang Huo, Hubei, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/76 (2006.01); H10B 43/27 (2023.01); H01L 21/762 (2006.01); H01L 21/768 (2006.01); H01L 23/48 (2006.01); H01L 23/522 (2006.01); H10B 43/30 (2023.01); H10B 43/40 (2023.01);
U.S. Cl.
CPC ...
H10B 43/27 (2023.02); H01L 21/76224 (2013.01); H01L 21/76877 (2013.01); H01L 23/481 (2013.01); H01L 23/5226 (2013.01); H10B 43/30 (2023.02); H10B 43/40 (2023.02); H01L 21/76802 (2013.01); H01L 21/76898 (2013.01);
Abstract

A method for forming a gate structure of a 3D memory device is provided. The method comprises: forming a plurality of hybrid shallow trench isolation structures in a substrate, each hybrid shallow trench isolation structure comprising a dielectric sublayer and a conductive sublayer, both of which are embedded in the substrate; forming an alternating dielectric stack on the substrate; forming a slit penetrating vertically through the alternating dielectric stack and extending in a horizontal direction to expose a row of hybrid shallow trench isolation structures; forming a plurality of array common source contacts in the slit, each array common source contact being in electric contact with a corresponding hybrid shallow trench isolation structure.


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