The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 24, 2023

Filed:

Sep. 04, 2020
Applicants:

United Microelectronics Corp., Hsin-Chu, TW;

Fujian Jinhua Integrated Circuit Co., Ltd., Quanzhou, CN;

Inventors:

Chun-Chieh Chiu, Keelung, TW;

Pin-Hong Chen, Tainan, TW;

Yi-Wei Chen, Taichung, TW;

Tsun-Min Cheng, Changhua County, TW;

Chih-Chien Liu, Taipei, TW;

Tzu-Chieh Chen, Pingtung County, TW;

Chih-Chieh Tsai, Kaohsiung, TW;

Kai-Jiun Chang, Taoyuan, TW;

Yi-An Huang, New Taipei, TW;

Chia-Chen Wu, Nantou County, TW;

Tzu-Hao Liu, Taichung, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/49 (2006.01); H01L 21/28 (2006.01); H01L 21/02 (2006.01); H01L 21/3213 (2006.01); H01L 29/423 (2006.01); H10B 12/00 (2023.01); H01L 21/285 (2006.01);
U.S. Cl.
CPC ...
H01L 29/4941 (2013.01); H01L 21/02532 (2013.01); H01L 21/02592 (2013.01); H01L 21/28052 (2013.01); H01L 21/28061 (2013.01); H01L 21/3213 (2013.01); H01L 29/42372 (2013.01); H10B 12/05 (2023.02); H10B 12/482 (2023.02); H01L 21/28518 (2013.01); H01L 21/28556 (2013.01); H10B 12/30 (2023.02);
Abstract

A method for fabricating semiconductor device includes the steps of first forming a silicon layer on a substrate and then forming a metal silicon nitride layer on the silicon layer, in which the metal silicon nitride layer includes a bottom portion, a middle portion, and a top portion and a concentration of silicon in the top portion is greater than a concentration of silicon in the middle portion. Next, a conductive layer is formed on the metal silicon nitride layer and the conductive layer, the metal silicon nitride layer, and the silicon layer are patterned to form a gate structure.


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