The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 24, 2023

Filed:

May. 28, 2021
Applicant:

Kla Corporation, Milpitas, CA (US);

Inventors:

Robert J. Rathert, Mechanicsville, VA (US);

David W. Price, Austin, TX (US);

Chet V. Lenox, Lexington, TX (US);

Oreste Donzella, San Ramon, CA (US);

Kara L. Sherman, San Jose, CA (US);

John Robinson, Austin, TX (US);

Assignee:

KLA Corporation, Milpitas, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/67 (2006.01); G05B 19/418 (2006.01); G01R 31/26 (2020.01);
U.S. Cl.
CPC ...
H01L 21/67288 (2013.01); G01R 31/2601 (2013.01); G05B 19/41875 (2013.01); G05B 2219/45031 (2013.01);
Abstract

Systems and methods for semiconductor adaptive testing using inline defect part average testing are configured to receive a plurality of inline defect part average testing (I-PAT) scores from an I-PAT system, where the plurality of I-PAT scores is generated by the I-PAT system based on semiconductor die data for a plurality of semiconductor dies, where the semiconductor die data includes characterization measurements for the plurality of semiconductor dies, where each I-PAT score of the plurality of I-PAT scores represents a weighted defectivity determined by the I-PAT system based on a characterization measurement of a corresponding semiconductor die of the plurality of semiconductor dies; apply one or more rules to the plurality of I-PAT scores during a dynamic decision-making process; and generate one or more adaptive tests for at least one semiconductor die of the plurality of semiconductor dies based on the dynamic decision-making process.


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