The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 24, 2023

Filed:

Feb. 04, 2021
Applicant:

Micron Technology, Inc., Boise, ID (US);

Inventors:

Jung Sheng Hoei, Newark, CA (US);

Sampath K. Ratnam, Boise, ID (US);

Renato C. Padilla, Boise, ID (US);

Kishore K. Muchherla, Fremont, CA (US);

Sivagnanam Parthasarathy, Carlsbad, CA (US);

Peter Feeley, Boise, ID (US);

Assignee:

Micron Technology, Inc., Boise, ID (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 11/10 (2006.01); G06F 3/06 (2006.01); G11C 11/56 (2006.01); G11C 16/04 (2006.01); G11C 29/00 (2006.01); H10B 43/27 (2023.01); G11C 29/52 (2006.01);
U.S. Cl.
CPC ...
G06F 11/1072 (2013.01); G06F 3/064 (2013.01); G06F 3/0608 (2013.01); G06F 3/0619 (2013.01); G06F 3/0625 (2013.01); G06F 3/0688 (2013.01); G06F 11/10 (2013.01); G06F 11/1076 (2013.01); G11C 11/5642 (2013.01); G11C 29/52 (2013.01); G11C 29/74 (2013.01); H10B 43/27 (2023.02); G11C 16/0483 (2013.01); Y02D 10/00 (2018.01);
Abstract

The present disclosure includes a redundant array of independent NAND for a three dimensional memory array. A number of embodiments include a three-dimensional array of memory cells, wherein the array includes a plurality of pages of memory cells, a number of the plurality of pages include a parity portion of a redundant array of independent NAND (RAIN) stripe, and the parity portion of the RAIN stripe in each respective page comprises only a portion of that respective page.


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